Static, random access memories (SRAMs) employ a number of cells, each for storing a single binary bit of information. Typical SRAM cell structures include what is commonly referred to as a four transistor, two resistor (4T-2R) SRAM cell and what is commonly referred to as a six transistor (6T) SRAM cell. A (4T-2R) SRAM cell is illustrated in (prior art) FIG. 1 of the drawing generally designated by the number 100. SRAM cell 100 is shown to include four, N-channel, transistors, which are designated 110, 112, 114, and 116, and two (load) resistors, which are designated 120 and 122. Transistor 110 is configured as a transfer transistor with the source (or drain) (end of the channel) of the transistor connected to an (active-high) bit (input/-output) line (BL), which is designated 130. The gate of transistor 110 is connected to an (active-high) word (control) line (WL), which is designated 132. The drain (or source) (end of the channel) of transistor 110 is coupled by resistor 120 to a power supply potential (Vcc), which is represented by a line 134. Transistor 112 is configured as a pull-down transistor with the transistor source connected to circuit ground (Vss), with the transistor gate coupled by resistor 122 to power supply line 134, and with the transistor drain connected to the drain of transistor 110. Transistor 114 is also configured as a pull-down transistor with the transistor source connected to circuit ground, with the transistor gate connected to the drain of transistor 110, and with the transistor drain connected to the gate of transistor 112. Finally, transistor 116 is, also, configured as a transfer transistor with the transistor source connected to the gate of transistor 112, with the transistor gate connected to word line (WL) 132, and with the transistor drain connected to an (active-low) bit (input/output) line (/BL), which is designated 140. The lines connecting the cross-coupling gates and drains of the pull-down transistors are designated 150 and 152.
A six transistor (6T) SRAM cell is illustrated in (prior art) FIG. 2 generally designated by the number 200. SRAM cell 200 is shown to include four, N-channel, transistors, which are designated 210, 212, 214, and 216, and two, P-channel, (load) transistors, which are designated 220 and 222. The transistors are configured with the source of transistor 210 connected to an (active-high) bit (input/-output) line (BL), which is designated 230, with the transistor gate connected to an (active-high) word (control) line (WL), which is designated 232, and with the transistor drain connected to a node which is connected to the source of transistor 220, to the drain of transistor 212, and to the gate of both transistors 214 and 222. Connected to another node is the gate of both transistors 220 and 212, the source of transistor 222, the drain of transistor 214, and the source of transistor 216. The drain of both transistors 220 and 222 are connected to a power supply potential (Vcc), which is represented by a line 234; and, the source of both transistors 212 and 214 are connected to circuit ground (Vss). The gate of transistor 216 is connected to word line (WL) 232; and, the drain of the transistor is connected to an (active-low) bit (input/output) line (/BL), which is designated 240.
In the implementation of high density SRAMs, the cell size is one of the more critical parameters, as it determines the total area of the memory array and, therefore, the chip size. Heretofore, for poly-silicon-resistor load (4T-2R) SRAM cells, in the conventional planar layout, the size of the pull-down transistor (114) has accounted for a significant portion of the cell area. This is because, heretofore, the pull-down transistor (114) size had to be around three times that of the transfer transistor (116) to prevent the state of the cell from being upset when transfer transistor (116) is turned on when the state of the cell is being read.
The reader may find of interest the U.S. Pat. Nos. 4,794,561 and 4,876,215 of Fu-Chieh Hsu.